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IC EEPROM 64K 150NS SO-28

The AT28C64E-15SC is one member of the AT28C64 series.The AT28C64 is a low-power, high-performance 8,192 words by 8 bit nonvolatile Electrically Erasable and Programmable Read Only Memory with popular, easy to use features.The device is manufactured with Atmel’s reliable nonvolatile technology.Atmel's 28C64 has additional features to ensure high quality and manufacturability. The device utilizes error correction internally for extended endurance and for improved data retention characteristics. An extra 32-bytes of E2PROM are available for device identification or tracking.

Features of the AT28C64E-15SCare:(1)fast read access time - 120 ns; (2)fast byte write - 200 μs or 1 ms; (3)self-timed byte write cycle:internal address and data latches,internal control timer,automatic clear before write; (4)direct microprocessor control:READY/BUSY open drain output.DATA polling; (5)low power:30 mA active current,100 μA CMOS standby current; (6)5V ±10% supply; (7)CMOS and TTL compatible inputs and outputs; (8)JEDEC approved byte-wide pinout; (9)commercial and industrial temperature ranges.

The absolute maximum ratings of the AT28C64E-15SC can be summarized as:(1)all input voltages(including NC pins)with respect to ground:-0.6 to 6.25V;(2)storage temperature:-65 to 150℃;(3)temperature under bias:-55 to 125℃;(4)all output voltages with respect to ground:-0.6 to Vcc+0.6V;(5)voltage on OE and A9 with respect to ground:-0.6 to 13.5V;(6)digital input voltage:-0.7 to (VA+)+0.7V.Stresses beyond those listed under"Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.The AT28C64 is accessed like a Static RAM for the read or write cycles without the need for external components.During a byte write, the address and data are latched internally, freeing the microprocessor address and data bus for other operations. Following the initiation of a write cycle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer.